Analog Input Voltage

The basics

Bob Meddins , in Introduction to Digital Signal Processing, 2000

The anti-aliasing filter

If the analogue input voltage is not sampled frequently enough then this results in something of a shambles. Basically, high frequency input signals will appear as low frequency signals at the output, which will be very confusing to say the least! This phenomenon is called aliasing. In other words, the high frequency input signals take on another identity, or 'alias', on leaving the system.

To get a feel for the problem of aliasing, consider a sinusoidal signal, of fixed frequency, which is being sampled every 7/8 of a period, i.e. 7T/8 (Fig. 1.5). Having only the samples as a guide, it can be seen that the sampled signal appears to have a much lower frequency than it really has.

Figure 1.5.

In practice, a signal will not usually have a single frequency but will consist of a very wide range of frequencies. For example, audio signals can contain frequency components in the range of about 20 Hz to 20 kHz.

To prevent aliasing, it can be shown that the signal must be sampled at least twice as fast as the highest frequency component.

This very important rule is known as the Nyquist criterion, or Shannon's sampling theorem, after two distinguished pioneers from the world of signal processing.

If this sampling rate cannot be achieved, perhaps because the components used just cannot respond this quickly, then a lowpass filter must be used on the input end of the system. This has the job of removing signal frequencies greater than f s/2, where f s is the sampling frequency. This is the role of the anti-aliasing filter. An anti-aliasing filter is therefore a lowpass filter with a cut-off frequency of f s/2.

The important frequency of f s/2 is usually called the Nyquist frequency.

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Interfacing Digital Logic to the Real World: A/D Conversion, D/A Conversion, and Power Electronics

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

8.3.2 ADC Characteristics

The ADC analogue input (voltage or current) can vary from a set minimum value to a set maximum value to provide a valid digital output representation of the analogue input. Any analogue input that exceeds these limits (both positive and negative inputs) can damage the ADC as well as saturate the output at a minimum or maximum digital output value. It is common for the ADC output to be an unsigned binary value, although (particularly for bipolar operation) the digital output might also be provided in signed binary (2s complement) representation.

The digital output is a discrete level signal with a value that represents a range of analogue input signal levels. As such, there will be a quantization of the analogue input signal. The ADC creates a quantization error that results from the conversion of the infinitely variable analogue input signal to a discrete level output signal. This quantization error will be important to the choice of the ADC resolution (number of bits). The higher the resolution of the ADC for a given input signal range, the smaller the quantization error as the number of possible output codes for the given input signal range increases. This effect is sometimes referred to as a many-to-one mapping.

The conversion process can be considered with the generalized form shown in Figure 8.22. In this model, two main operations are identified, the sampling operation and the quantization operation.

Figure 8.22. Generalized A/D conversion

The analogue input signal is sampled using an ideal sampling block at a sampling rate (sampling frequency) of fS Hz. The process converts a continuous time signal into a discrete time signal. The sampled signal is then fed to a quantization block that produces the digital output x(n) where n indicates the sample number, as well as process produces quantization noise.

Both ideal and real characteristics of the ADC must be considered. An ideal ADC identifies the operation of the ADC when all values are set to their designed (or ideal) values. However, due to manufacturing tolerances of the ADC circuitry, real ADC operation deviates from the ideal. In this case, the ADC maximum deviation is defined in the ADC data sheet and guaranteed by the manufacturer. To understand the operation of the ADC, it is common to begin by considering the ideal ADC and then identify how a real ADC could deviate from this.

Consider a three-bit ADC (for simplicity) with an input voltage that ranges from 0 V to + 5.0 V and an unsigned binary output code. This is a unipolar ADC whose input voltage ranges from 0 V to the full-scale voltage (VFS). The output code ranges from 0002 (010) to 1112 (710). The ideal ADC transfer curve, the input voltage–output code relationship, is shown in Figure 8.23. In this view, the input signal conversion range (from the minimum input voltage value 0 V to the maximum input voltage value VFS) is divided into 2n, where n is the ADC resolution (number of output bits) equal segments, and the point at which the output code moves from one value to the next value falls in the middle of each segment (except for the end points). For a three-bit ADC, the voltage range is split into eight equal segments. For an eight-bit ADC, the voltage range is split into 256 equal segments. A change in 1 LSB of the input voltage creates a step change in the output code of 1 bit. For each 1 LSB step change in the input voltage, the voltage level range is given by:

Figure 8.23. ADC transfer curve

V LSB = ( 2 - n ⋅ V FS )

V LSB = ( 2 - 3 × 5 .0 )

V LSB = ( 0 .125 × 5 .0 ) = 0 .625 V

The width of a segment is 1 LSB. The point at which the output code changes from one value to the next is the code transition point. When the output code is 0002, the code changes to 0012 in the middle of the segment, and the width of this code is ½ LSB. When the output code is 1102, the code changes to 1112 in the middle of the segment, and the width of the final code is 1½ LSBs. For an ideal ADC, the corner points at the code transition points can be joined with a straight line. Nonideal converters have characteristics that deviate from this straight line.

The input voltage transition point to output code values are shown in Table 8.9.

Table 8.9. Ideal three-bit ADC input voltage to output code mapping (1 LSB = 0.625 V)

Code transition point Input voltage at code transition point (V) Output code (binary) Output code (decimal equivalent)
Minimum input voltage 0.0 000 0
1st code transition point 0.3125 001 1
2nd code transition point 0.9375 010 2
3rd code transition point 1.5625 011 3
4th code transition point 2.1875 100 4
5th code transition point 2.8175 101 5
6th code transition point 3.4375 110 6
7th code transition point 4.0625 111 7
Full-scale voltage 5.0 111 7

As the resolution (number of bits) of the converter increases and the operating voltage range of the ADC decreases, the LSB step size (voltage or current) will decrease. The effect of this is that the analogue signal levels become the same order of value as the noise generated in the circuit, and the inevitable manufacturing process variations have a more significant impact, leading to problems with design and ultimate use of these converters. Unwanted circuit effects not seen with the lower-resolution data converters are then seen with the higher-resolution data converters.

The characteristics of the ADC are categorized into three types of parameters—static (DC) parameters, transfer curve parameters, or dynamic parameters—whose details are specified in the tables that follow.

The static (DC) and transfer curve parameters are closely related and are considered here together in Table 8.10.

Table 8.10. Static (DC) and transfer curve parameters

Parameter number Parameter name Parameter description
1 DC gain error A measure of the deviation of the slope of the straight-line approximation of the actual converter output from the ideal converter straight-line output. The best-fit straight-line approximation is used for the actual converter straight-line approximation.
2 Offset The deviation of the first code transition point from the expected. The ideal converter or best-fit straight-line approximation is used. This is normally quoted in LSBs.
3 Integral nonlinearity (INL) A measure of the deviation of the actual converter code transition point from the straight-line approximation for each code. The best-fit straight-line approximation is used. This is normally quoted in LSBs.
4 Differential nonlinearity (DNL) The difference between the width (range of input signal) between converter output code changes and an ideal step size of 1 LSB. For a given input code, the output step size is taken between the current input code and the previous code. This is normally quoted in LSBs.
5 Monotonicity The output code should increase with an increase in input signal; this is a monotonic ADC. A nonmonotonic ADC has an output code that decreases (at particular codes) as the input signal increases.
6 Missing codes The converter output (digital) should generate 2n codes where n is the resolution of the converter. Problems may occur within the converter where certain codes are not generated.

The static and transfer curve tests do not look at the dynamic operation of the ADC and the effects of signal changes and frequency related effects. The dynamic parameters, identified in Table 8.11, describe these effects.

Table 8.11. Dynamic parameters

Parameter number Parameter name Parameter description
1 Conversion time There must be a guaranteed maximum conversion time (time from start of conversion to conversion completed).
2 Recovery time Some ADCs require a minimum time after a conversion has been completed before the next conversion may start.
3 Sampling frequency Testing of ADC at maximum sampling frequency and ensuring that no errors occur.
4 Aperture jitter Variations in the sampling period cause an error in the digitized value. Aperture jitter will add noise to the digitized signal.
5 Sparkling Results from digital timing race conditions. The ADC occasionally produces an output with a larger than expected offset error.

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PCB Design

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

3.5.7 Analogue I/O Board

The analogue I/O board generates and samples analogue voltages under the control of the CPLD (Figure 3.27).

Figure 3.27. Analogue I/O board block diagram

A stereo DAC (digital-to-analogue converter) provides two analogue output voltages digitally generated by the CPLD. The DAC is a Wolfson® Microelectronics WM8725 stereo DAC with a serial interface, which requires seven digital signals for control and data, analogue and digital power supplies, and an analogue reference voltage. A stereo ADC (analogue-to-digital converter) is used to sample two analogue input voltages into the CPLD. The ADC is a Wolfson® Microelectronics WM8738 stereo ADC with a serial interface, which requires six digital signals for control and data, analogue and digital power supplies, and an analogue reference voltage.

Table 3.14 identifies the component list for the analogue I/O board.

Table 3.14. Analogue I/O board component list

Component no. Component description Quantity
1 20-way IDC plug (PCB mount) 1
2 150 W resistor (0.6 W, ±1% tolerance) 5
3 1 MW resistor (0.6 W, ±1% tolerance) 2
4 Blue LED (20 mA) 1
5 Red LED (20 mA) 2
6 Green LED (20 mA) 2
7 1N4001 diode 5
8 WM8725 stereo DAC 1
9 WM8738 stereo ADC 1
10 REF3230 (3.0 V) voltage reference IC 1
11 LM324 quad op-amp 1
12 PCB mount BNC connector 4
13 PCB mount screw terminal (3-way) 1
14 10 µF electrolytic capacitor 5
15 100 nF ceramic capacitor 6
16 Eyelet test probe point 6

Table 3.15 identifies the 20-way IDC connector pin allocation for the analogue I/O board.

Table 3.15. Analogue I/O board 20-way IDC connector pin allocation

Pin no. Identifier Function Direction
1 VDD +3.3 V DC Power supply
2 ADC_FMT WM8738 ADC signal FMT Input
3 ADC_NOHP WM8738 ADC signal NOHP Input
4 ADC_SDATO WM8738 ADC signal SDATO Output
5 ADC_LRCLK WM8738 ADC signal LRCLK Input
6 ADC_BCLK WM8738 ADC signal BCLK Input
7 ADC_MCLK WM8738 ADC signal MCLK Input
8 DAC_FORMAT WM8725 DAC signal FORMAT Input
9 DAC_SCKI WM8725 DAC signal SCKI Input
10 DAC_LRCIN WM8725 DAC signal LRCIN Input
11 DAC_DIN WM8725 DAC signal DIN Input
12 DAC_BCKIN WM8725 DAC signal BCKIN Input
13 DAC_DEEMPH WM8725 DAC signal DEEMPH Input
14 DAC_MUTE WM8725 DAC signal MUTE Input
15 — — —
16 ADC_1_LED ADC input 1 selected indicator LED Input
17 ADC_2_LED ADC input 2 selected indicator LED Input
18 DAC_1_LED DAC input 1 selected indicator LED Input
19 DAC_2_LED DAC input 2 selected indicator LED Input
20 VSS 0 V DC Power supply

Both the DAC and the ADC require a reference voltage to operate. This is externally generated using a Reference Voltage IC (REF3230), which provides an accurate +3.0 V voltage to supply the analogue power to both the DAC and ADC, which in turn internally generates the required reference voltage.

Each of the analogue inputs and outputs to and from the board are connected via an op-amp operating as a unity gain buffer to BNC connectors on the board. The output voltage range is set by the output range of the DAC (minimum to maximum output voltage values) and the input range of the ADC (minimum to maximum input voltage values). The outputs and inputs are also unipolar (positive voltages only).

Therefore, for bipolar (positive and negative voltages) and for a wider range of I/O voltages, external circuitry is required to appropriately condition the signals.

Four yellow LEDs are also mounted on the PCB so the CPLD can indicate which DAC or ADC is actually selected at any one time.

The circuit requires a +3.3 V digital power supply via the IDC connector from the CPLD development board to provide the necessary power to the buffer ICs. A protection diode (1N4001) is reversed-biased across the power supply so that when the power supply is connected in the correct orientation, the diode does not have any effect. If, however, the power supply orientation is reversed (i.e., +3.3 V and 0 V are connected the wrong way around), then the diode will conduct and for a short time until it is damaged, then the IC VDD will be limited to approximately −0.6 V (because of the forward-biased diode voltage drop), and during this time, the ICs will be protected from damage resulting from electrical overstress.

The analogue power for the op-amps is provided by a separate screw terminal connector. This additional power supply also incorporates protection diodes.

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Instrumentation and interfacing

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. WOODS MA, DPhil , in Digital Logic Design (Fourth Edition), 2002

10.8 A/D converter types using an embedded D/A converter

Another class of A/D converter is built around a D/A converter which undertakes the opposite conversion to that actually required (see Figure 10.9). Every time an A/D conversion is needed, a conventional binary counter is cleared and starts counting up from the starting value of (0)2. The digital outputs of the binary counter are directly connected to the embedded D/A converter, so the output from this converter is an analogue voltage that rises steadily (in 'staircase' fashion) from 0 V. An analogue comparator continuously compares the output voltage from the embedded D/A converter with the analogue input voltage; at the exact instant that the output voltage from the embedded D/A converter has risen above the analogue input voltage, the counter's digital output value is stored in a set of D-type flip-flops. This D-type register must therefore now contain the digital equivalent output of the analogue input. This type of converter is quite slow as each conversion takes at least the time required for the counter to count from (0)2 to the binary equivalent of the input analogue voltage (and potentially to the maximum binary output). However, the complexity of the flash converter is avoided. This type of A/D converter may operate faster than an integrating type, since the conversion period is not tied to the mains supply cycle, but does not have the advantage of rejecting mains-synchronous interference. In principle, the integrating type of A/D converter can also operate faster than is necessary to suppress mains-borne interference, but this would discard the great advantage of this type of converter.

Figure 10.9. The principle of the A/D converter using an embedded D/A converter

There are two important variations of this type with an embedded D/A converter. In the first variation, the counter is not reset to (0)2 at each conversion request, but instead the comparator is used to indicate whether the analogue input voltage is greater or less than the output from the embedded D/A converter retained from the previous conversion, and the counter then counts up or down, as appropriate, from the previous count value. If the input voltage has not changed very greatly from the time of the previous conversion, i.e. the input voltage is slowly varying and/or A/D conversions are required on a regular basis, then this modification offers the advantage of reduced conversion time. However, if the input voltage cannot be assumed to be slowly varying, or if conversions are only required on an irregular basis, then in principle the time taken for a new A/D conversion will still be equal to the time taken for the counter to count from (0)2 to the maximum binary count value, i.e. the worst case conversion time. This disadvantage may be alleviated by arranging for internal conversions to be made continuously, but when an external conversion request is received, the conversion cycle restarts immediately with the counter starting from its current value.

In the second variation of the basic A/D converter with an embedded D/A converter, a binary counter is not used but instead is replaced by an n-bit digital storage register in which each of the n bits may be independently set or cleared under control of some extra logic. The basic principle is illustrated in the block circuit diagram shown in Figure 10.10, and a typical voltage waveform at the output of the embedded D/A converter is shown in Figure 10.11 in the case of a simple 3-bit converter. In this simple example, the 3-bit D/A converter has 23 = 8 possible output voltages ranging from 0 up to 7 times its basic output unit. Rather than having a counter starting to count from (0)2 towards the final base 2 digital equivalent of the analogue input, the control logic first clears to 0 all the bits of the storage register except the MSB which is set to 1. Therefore, the output of the embedded D/A converter will be close to half its maximum value. The output is not exactly half because, as an example for the case of a 3-bit register, the maximum output from the embedded D/A converter is (111)2 = (7)10, whereas just setting the MSB to 1 as set up by the control logic gives the output (100)2 = (4)10. Then, the comparator is used to determine whether the embedded D/A converter is giving an output greater or less than the analogue input; if the embedded D/A converter is giving an output greater than the analogue input then the MSB is cleared to 0, but if not, the MSB is left at the value 1. At this stage, therefore, the control logic has adjusted the MSB to the correct value, and so moves on to the next most significant bit. The control logic sets this bit to 1 and again uses the comparator to determine whether the embedded D/A converter is now giving an output greater or less than the analogue input. If the embedded D/A converter output is greater than the analogue input, this bit is cleared to 0; if less than the analogue input, then this bit is left at 1. The control logic then moves on to the other bits in turn in order of their numerical significance, i.e. their position in the binary integer. This type of A/D converter is called a 'successive approximations' converter, as the converter is successively making better and better approximations to the final value of the digital output.

Figure 10.10. The principle of the 'successive approximations' A/D converter

Figure 10.11. Typical waveform produced by the embedded D/A converter in a 'successive approximations' A/D converter

The advantage of the successive approximations A/D converter over the type using a counter is that it implements a binary search for the digital equivalent value of the analogue input, rather than a sequential search starting either from (0)2 or from the previous output value. A binary search is a much more efficient method of finding an unknown value than a sequential search, and so in general the conversion times using a successive approximations converter will be much less than those achieved with a counter-type converter. This may be understood by examining the number of voltage comparisons needed for each A/D conversion. For an n-bit output, a successive approximations converter needs to undertake n comparisons per conversion, one for each bit. By contrast, the number of comparisons per conversion required by the counter type will range from 1 at minimum up to a maximum of 2 n − 1. Since the number of required comparisons varies widely in the case of the counter type, occasionally the counter type will be faster than the successive approximations type. However, if any allowable value of the analogue input voltage is equally likely, and if the counter is reset for each conversion, then on average the number of comparisons required by the counter type is (2 n )/2 = 2 n−1, which will always be greater than the n comparisons required by a successive approximations converter, assuming that A/D conversions of more than n = 2 bits are needed.

The counter type where the counter is not reset for each conversion may operate much faster under favourable conditions, i.e. if conversions are required so frequently that the required output changes by no more than (1)10 or (2)10 or so at each conversion. However, if the input is varying so rapidly that there is no similarity between successive input voltages at the sampling times, or if any value of the analogue input voltage within the allowable conversion range is equally likely, then the average number of comparisons required per conversion will be approximately (2 n )/4 = 2 n−2, the same as for a counter type where the counter is reset to a value midway between minimum and maximum counts prior to either up or down counting under control of the comparator.

Note that in the case of the successive approximations A/D converter (unlike the type with a counter driving an embedded D/A converter), there is no advantage to be gained in not clearing the register before each conversion; each conversion still requires each of the n bits to be examined in turn. The equal conversion times from a successive approximations converter is a major advantage in certain applications where the variable conversion times from the counter types (and potentially very long conversion times when the counter must count over all or nearly all of its range) cannot be tolerated.

The familiar Compact Disc (CD) digital audio format stores analogue audio signals in the form of an optically-readable stream of digital values sampled regularly at 44.1kSa/s. It requires 16-bit conversions, A/D in recorders or D/A in CD players. However, professional-quality digital recorders will record at 20 or 24 bits (or greater resolution) and at greater conversion rates, partly so as to be compatible with improved digital formats, but mainly so that, on copying the master studio recording to the final CD, the recording level (i.e. the amplitude of the final analogue signal) may be increased to some extent if necessary while still maintaining at least 16-bits resolution in the digital information recorded on CD. The design of such high-resolution converters and their associated circuitry is not straightforward, because of the need for the analogue parts of the system to operate to the same precision or better. Although the standard CD format provides only 16-bit sampling precision, some CD players use various advanced techniques to increase the effective number of bits available for converting to the analogue signal, by reconstructing extra digital information according to some assumptions made about the nature of the audio signal, and the use of other digital signal-processing techniques. These players undertake D/A conversion at higher rates (known as oversampling), in attempts to increase the accuracy of the reconstructed audio signal. Similar principles are used in the design of digital audio tape (DAT) recorders and players. The required conversion rate prevents the use of integrating types of A/D converter in recorders, and the precision necessary prevents the use of flash converters. On the other hand, for digital video discs and tapes the bandwidth required is much greater (5.5MHz bandwidth for a typical conventional video signal, requiring a minimum sampling rate of 11MSa/s) but the necessary precision is poorer (8 bits per sample is usually ample for video information, because of the greater noise tolerance of the eye than the ear). Therefore, for digital video, if no data compression techniques are used, it would be necessary to record and reproduce of the order of 88 Mbit/s plus the bit rate needed for the accompanying audio and control signals, compared to the 1.4Mbit/s for 2-channel 16-bit audio at 44.1kSa/s. For this reason, the technical requirements for digital video are considerably more exacting than for digital audio, and commercial digital video systems have only been available since the mid-1990s. Even so, current digital video systems use some data compression techniques to reduce the necessary bit rate, whereas domestic digital audio has been a practical reality since the early 1980s. At the highest conversion rates, self-contained IC A/D converters capable of operating at 1GSa/s with 6- or 8-bit resolution are now readily available.

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PIC16 C Applications and Systems

Martin P. Bates , in Programming 8-bit PIC Microcontrollers in C, 2008

BASE Board

A general purpose board with a typical selection of peripherals attached to a PIC 16F877A is described here. This design was originally developed to demonstrate hardware interfacing techniques. The PIC 16F877 BASE (basic application and system evaluation) board incorporates six analog inputs, a 12-button keypad, a parallel 16 × 2 character LCD, 16   k serial memory, an RS232 port, and ICD programming connections. The block diagram is shown in Figure 5.3, the schematic in Figure 5.4.

Figure 5.3. BASE Board Block Diagram

Figure 5.4. BASE Board Circuit Diagram

Here, the board is used as a data logger. It records input analog voltage levels at timed intervals and stores this data for later uploading to a host PC. The PIC 16F877 has eight 10-bit analog inputs, but to keep the demo system simple, 8-bit conversion is used. The reference voltage applied to RA3 is 2.56   V, which gives a resolution of 2.56/256 = 10   mV per bit and a precision of 100/256 ≈ 0.4%.

The reference voltage and a test input occupy two of the analog inputs, so six are available for connecting to an external target system. Typically, the inputs are connected to analog sensor inputs, measuring temperature, position, strain, and other physical variables from suitable sensors. Another possibility is that the target system is an analog board whose performance is being evaluated by measuring the circuit voltages under test conditions.

The measured values are stored in an I2C serial flash memory chip, which retains the data when powered down. The driver routines for this device are demonstrated in section 3.6. The data can be transferred later to a host PC or other data terminal via the RS232 interface. A driver chip is fitted to convert the data to line voltages.

The board has a simple keypad, where operational parameters, such as the sampling interval, can be input during initialization or the mode of operation toggled between "logging" and "uploading." Scanning a keypad is described in section 2.6 in connection with the calculator demo application.

The parallel LCD is used to display status messages and data as they are sampled. It is useful to compare it with the serial LCD described previously, as parallel access is generally faster, particularly when bit maps are used for graphics in more sophisticated applications. The 8-bit ASCII and control codes must be sent as 4-bit nibbles from RD4-7, with RD1 acting as the register select (RS) input and RD2 generating the data strobe (E). More details are provided on driving the parallel LCD in Interfacing PIC Microcontrollers, by the author. Alternatively, the manufacturer's data sheet can be consulted for the necessary control codes and timing information.

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